Moshe Gavrielov
Analyst · Sandeep Shyamsukha of Auriga USA
Thank you, Jon, and good afternoon to you all. Our 5% increase in revenue in the June quarter was driven by the fact that 7 of our secondary end market segments grew sequentially by double digits. This very broad-based end market strength resulted in revenue growth that exceeded the high end of our revenue guidance and speaks to the continued displacement of ASICs and ASSPs by PLD. In the June quarter, new product sales drove our growth with a 17% increase. A portion of this is attributable to our 65-nanometer Virtex-5 family to increase 15% during the quarter. This is driven by applications in wired and wireless communications, image processing and storage. This family remains the industry's largest FPGA family, in terms of quarterly sales with ongoing design win momentum well beyond initial projection. Notwithstanding the unparalleled success of Virtex-5 in the market, it's worth -- it is worth noting that cumulative sales of Virtex-6 actually surpassed the cumulative sales of the Virtex-5 family the same point in its life cycle. I'm very pleased this combined sales for our 40-nanometer Virtex-6, 45-nanometer Spartan-6 products grew by more than 40% and now represent nearly 10% of total company revenue. We expect these families to experience significant growth in the September quarter as well based on customer forecasts. We continue to see strong design win momentum in our 40, 45-nanometer family. Virtex-6 family provides our customers with significantly lower power, lower costs and up to 12 gigabit per second transceivers. Spartan-6 family continues to be the only 40 and 45-nanometer low cost offering from major FPGA vendor enabling 40% lower power, 10% performance advantages with up to 3 gigabit per second integrated transceivers in a low cost device. Our 28-nanometer product family roll out continues at an accelerated pace. Last month, we sampled the first device from our Virtex-7 product family. Coupled with Kintex-7, which was the industry's first 28-nanometer product which we sampled in the first calendar quarter of the year, we have now sampled members from 2 of our 428-nanometer product families and in addition, taped out the core technologies for a stacked silicon interconnect based offering. We are also the first to deliver full year release 28-nanometer design software supporting all families. To enhance the design process, we recently released our ISE Design Suite 13.2 which provides increased design of productivity, proved quality of result for our 28-nanometer 7 series families, including the Virtex-7 2000T device, the industry's largest density FPGA both using stacked silicon interconnect technology. We are confident that by early 2012, we will be sampling members from our entire 28-nanometer family. The roll out of our 28-nanometer family continues to be the fastest next-generation product roll-out in our history. We are exceptionally pleased with the design win activity of our 28-nanometer family, which significantly exceeds previous generations at the same point of product introduction and currently represents several hundreds of millions of dollars. Based on our leading customers' feedback I'm convinced that our 28-nanometer strategy most effectively addresses the 3 industry mandates: Scalability, optimization and integration. Scalability is enabled through our unified architecture which allows customers to gain their designs independent of FPGA family selection, reuse IP across the family. A key element of optimization is enabled by our world-class technology partnership with TSMC, now proven with actual silicon that the usage of the TSMC HPL process delivers superior performance with the industry's lower power. Further, 7 series optimization is provided with industry-leading connectivity, DSP memory solutions, each of which is tailored for the unique needs of different end markets. Finally, we've developed 3 leadership technologies for systems integration. First of these is the Zynq-7000 family. It's the first industry's extensible processing platform that integrates an ARM Cortex A9 processor-based system with a 28-nanometer low-power programmable logic. With the Altix family, we offer high-volume customers superior performance and lower power with a significant bill of material cost savings through the integration of programmable mixed-signal function. Lastly, with our stacked silicon interconnect technology have a superior strategy for integrating multiple dye for 2x total capacity and bandwidth relative to all alternatives in the market. I'm confident that Xilinx has clear technology leadership at the 28-nanometer node is the only venture currently addressing all 3 of the industry mandates; scalability, optimization and integration. We expect our innovative and differentiated product offering coupled with time to market leadership will enable us to accelerate our ASIC and ASSP share gains to gain future PLD share as well. The combination of the continued Virtex-5 design win strength beyond our initial projections, the rapidly accelerating 40, 45-nanometer momentum and now the fastest design win ramp in the history of the company with 7 series gives me tremendous confidence in the depth and breadth of our customer base and product portfolio. Let me now turn the call back to the operator to open it up for the Q&A session.