Lip-Bu Tan
Analyst · Bank of America Merrill Lynch
Good afternoon, everyone, and thank you for joining us. I'm pleased to report that our strong momentum in Q1 continued into Q2. For the second quarter, revenue totaled $283 million, non-GAAP operating margin was 17%, and we generated $69 million of operating cash flow. Demand for both our software and hardware products was strong, driving increased run rates on renewals. For example, 2 of the world's top 10 semiconductor companies significantly increased their usage of our digital products. Both of these transactions consist primarily of new business, and together, will provide more than $10 million of incremental annualized revenue. And now let me turn to the second quarter by highlighting each of the 3 businesses: System Realization, SoC Realization and Silicon Realization. In Q2, we extended our position in System Realization with the launch of the System Development Suite. This new suite of products reduced system integration time by up to 50% by enabling hardware-software co-design within a common design environment. It introduced 2 new platforms: the Virtual System Platform and Rapid Prototyping Platform. These are tightly integrated with the 2 established platforms, the Palladium XP Verification Computing Platform and our Incisive Verification Platform. A number of leading customers and partners announced their adoption of the suite, including ARM, NVIDIA and Western Digital. NVIDIA, a user of Cadence emulation products for many years, deploy the broader Cadence System Development Suite with elements such as Rapid Prototyping Platform, offering immediate value. Sales of our Palladium XP Verification Computing Platform, a key component of the System Development Suite, was strong again. In Q2, Marvell purchased Palladium XP and will use it for future projects. We are also seeing new and growing global demand as HiSilicon, a China-based provider of ASIC and solutions for communication network and digital media, adopted Palladium XP to speed integration and time-to-market. Now let me talk about our SoC Realization business. Cadence is the leader in Verification IP, or VIP. In Q2, we announced the availability of VIP for ARM new AMBA 4 protocol. This new VIP enables designers to verify the functionality of multiprocessor ARM Cortex-A15 designs, which are now being deployed in various mobile applications, including tablets and smartphones. We also announced close collaboration with TSMC that will strengthen our design IP. This extends an already close relationships and ensures the availability of IP that has been validated at the foundry. Next, I will highlight our Q2 Silicon Realization successes. As I said in the beginning, we significantly expanded our digital implementation position at 2 of the world's top 10 semiconductor companies as we displaced alternative suppliers. This illustrates the growing competitiveness of our end-to-end digital solution, especially for advanced node designs, where the optimization of power, performance and area is more complex than in previous generations. We improve our digital flow with the acquisition of Azuro. This technology, when integrated into our end-to-end digital flow will enhance our customers' ability to optimize power, performance, area of the most complex designs. We also acquired Altos Design Automations, whose tools enable fast, accurate characterizations of foundation IP, generating models used for SoC implementation. These models, when combined with our digital and custom analog flows, improve the quality of results by providing greater visibility into the effects of noise, timing and power at every phase of the design cycle. Our customers tell me this a great acquisition for Cadence, and will significantly improve their implementation flows. In our Custom/Analog business, customer adoption of our Virtuoso 6.1 flow also continue to grow. We displaced a competitor analog flow at a leading 4G IC customer. We also announced that Bosch has standardized on our Virtuoso 6.1 technology, gaining an approximately 25% advantage in productivity. Finally, strong ecosystem partnerships are essential for the successful development and manufacturing of advanced SoC. I want to highlight key developments with several of our ecosystem partners this quarter. Samsung deployed the Cadence digital flow to tape out a test chip featuring an ARM processor at 20 nanometers. Cadence's Encounter-based digital flow was used to address the requirements of Samsung's advanced 20-nanometer process technology for the SOC. A number of new Cadence technologies has also been included in the new TSMC Reference Flow 12.0, and Analog/Mixed Signal Reference Flow 2.0. These include system level design capabilities available through our new System Development Suite. Cadence is currently also the only collaborating partner with TSMC to provide DFM service to their customers for TSMC 40-nanometer technology and below. Let me conclude my remarks with the following thoughts. We continue to see good momentum in our business. This quarter, we took an important step in building up our System Realization strategy to facilitate hardware-software system integration with the release of the System Development Suite. Key customers are selecting our digital solution for next-generation designs. The integration of our digital and custom analog solutions provides designers with powerful flow for mixed-signal SoC. We are investing in and strengthening our ecosystem partnerships. Now, Geoff will review the financial results and provide our outlook.