Lip-Bu Tan
Analyst · Cowen and Company
Good afternoon, everyone, and thank you for joining us. I'm pleased to report that Cadence finished a successful 2011 with a very strong Q4. For Q4, revenue totaled $308 million, non-GAAP operating margin was 21%, and we generated $62 million of operating cash flow. For the year 2011, revenue grew 23% to $1.15 billion, non-GAAP operating margin doubled to 18%, and operating cash flow totaled $240 million.
For 2012 we are forecasting revenue growth of approximately 8% to 11%. Geoff will present our full outlook in a few minutes.
Now I will recap our successes in 2011 and then provide some of our Q4 highlights. In 2011, Cadence demonstrated the readiness of our digital, custom, analog and signoff solutions for 22 -- 20-nanometer design. We completed 7 20-nanometer test chips with companies including ARM, Samsung, TSMC and other foundries and customers. Many more are in progress for 2012.
We established our product capabilities for designing SoC using advanced multi-core processors, including the first ARM Cortex-A15 test chip designed for the 20-nanometer TSMC silicon.
2011 was a stellar year for the Palladium XP Verification Computing Platform. An increasing numbers of customers, both semiconductor and system companies, now use Palladium to develop complex SoC and for hardware-software co-design.
Growing adoptions of our Encounter digital solution was highlighted in 2011 by key displacements at 2 major semiconductor companies and significant business wins at many other customers.
In 2011, our Virtuoso 6.1 strengthened its position as a platform of choice for doing custom and analog design. Virtuoso, based on the industry-standard open-access database, is enabling a paradigm shift from traditional connectivity-driven to a more automated constraint-driven methodology that is delivering a 2x productivity improvement.
To address the challenge of integrating hardware and software for complex systems, in 2011, we launched the System Development Suite. The suite includes 2 new products, the Virtual System Platform and Rapid Prototyping Platform, both of which are already in productions use at several customers. In 2011, we made 2 important acquisitions, Altos and Azuro. The Azuro technology is now offered with Encounter digital IC design platform and has been a critical factor in winning several design benchmarks. The products we acquired with Altos are recognized as the leading solutions for IP library, collectivization, helping customers produce higher-quality designs at advanced technology notes.
Now let us look at a few of the highlights for Q4. Business was strong across our Silicon Realization product line. In particular, I want to highlight our verification, mixed-signal and system -- silicon package for businesses. Today, every company doing advanced complex SoC, especially communication devices and embedded processor designs need more verification capability. Our Incisive Verification Platform is winning business and gaining share in advanced verification because of technology and methodology advantages. Incisive matrix-driven approach, multi-language support, mixed-signal and low-power features and tight connections with the Palladium XP and verification IP increase performance and productivity. Our verification business in Q4 was highlighted by a competitive displacement at one major semiconductor company and significant growth of our installed base with another.
Now turning to mixed-signal. In Q4, yet another company using Virtuoso for analog design adopted the Encounter digital IC design platform for their low-power and mixed-signal flow. This demonstrates the advantage of our end-to-end flow for low-power and mixed-signal design, which addresses the increasing complexity of digital content and mixed-signal design, as well the need for greater energy efficiency.
Our silicon package for business serves a wide spectrum of customers, large to small, in a variety of vertical market segments, including narrow [ph], networking infrastructures, medical, automotive and consumer electronics. The solution in our Allegro platform are compelling to customers because our tools enable increased design team productivity, have the technical capabilities to design the most complex ports and have links to leading mechanical CAD products. Our silicon package board business in Q4 included sales to several of the largest networking companies in the world.
Next, let us look at the SoC Realization. Our primary focus for IT continues to be on memory, storage and high-speed interfaces. The keys to our success are: We offer highly differentiated products; our focus on supporting the leading industry protocols and standards; and providing the highest performance products. Cadence has the leading DDR IP products, and we saw further adoption of this product in Q4.
We also announced the availability of the first combined controller and PHY IP solution that supports the open non-Flash interface 3.0 specification.
Q4 was a very strong quarter for Verification IP. In addition to facilitating SoC verification, Verification IP is increasingly used to verify and divide system connections between multiple chips and peripherals such as memory, camera and display. New protocols and increased time-to-market pressure for delivering end products are fueling the demand for our Verification IP by system and semiconductor companies.
Following the integration of Denali and Cadence VIP offerings, including providing support across all simulators, our VIP business grew over 40% in 2011. In System Realization, the Cadence Virtual System platform, part of the System Development Suite, is gaining traction for earlier software development.
We are collaborating with Xilinx to develop the first virtual platform for the Xilinx Zynq-7000 Extensible Processing Platform. The Zynq-7000 family of products combines an ARM dual-core Cortex-A9 with Xilinx 28-nanometer FPGA. A virtual platform for developing Zynq software application is built on the Cadence Virtual System Platform.
Let me conclude my remarks by pointing to what to expect in 2012 from Cadence. First, continued growth in our digital business as we build on our capabilities and success at 20-nanometer and with multi-core embedded processes. 20-nanometer will be -- also drive growth in our custom, analog and signoff platforms. Second, the strength of our integrated mixed-signal solution will attract more customers to choose Cadence flows. Third, increase the use of Cadence IP for memory, storage and high-speed interfaces and continue expansion of VIP business. And finally, further adoptions of our System Realization solution, building on the continued demand for Palladium XP.
With that, I will turn it over to Geoff who will review the financial results and provide our outlook.