Lip-Bu Tan
Analyst · Needham & Company
Good afternoon, everyone, and thank you for joining us today. Cadence delivered strong results for Q4. Revenue was $346 million. Non-GAAP operating margin was 23%, and operating cash flow was $96 million. For 2012, revenue grew 15% to $1.326 billion. Non-GAAP operating margin increased 5% points to 23%, and operating cash flow grew 31% to $316 million.
As we look at 2013, much like this time last year, semiconductor and global economic conditions are soft and uncertain. But for the most part, customers are continuing to invest in new designs. We also benefit from the increasing complexity of these designs. This ongoing design activity and our strong pipeline and backlog provide us with confidence in our Q1 and 2013 guidance. Geoff will discuss this later in the call.
First, let us start with highlights for Silicon Realization. In Q4, we extended our leadership in advanced node design. Cadence is working with leading ecosystem partners to implement test chips in preparation for customers designing for 14-nanometer and 16-nanometer FinFET processors. We've recently announced the success of 2 these projects. First, ARM, IBM and Cadence implemented 14-nanometer test chip featuring an ARM Cortex-M0 processor implemented using IBM 14-nanometer SOI FinFET processor. Second, ARM, Samsung and Cadence tape out the first ARM Cortex-A7 processor targeted at Samsung 14-nanometer FinFET process.
Cadence received a TSMC Partner of the Year Award for the 20-nanometer reference flow for digital, custom/analog and mixed-signal design. [indiscernible] improved performance by 57% on the 20-nanometer networking chip by using the Encounter flow. Virtuoso continues to be the gold standard for analog custom design and layout. The vast majority of users have successfully transitioned to the Virtuoso 6.1 product line, which is native on open access by industry standard database. This enables them to take advantage of improved automation and innovative capabilities, such as indesign signoff, which conducts checks on-the-fly to reduce layout iteration.
On Monday, Cadence introduced Virtuoso Advanced Node with breakthrough capabilities for design at 20-nanometer and below, including the support for layout-dependent effects, double patterning and FinFET readiness. Together, this improved productivity and shortened time-to-market for complex analog custom design.
With increasing integration of functionality and design, our customer expect continuous innovation in the capability and performance of Incisive, our verification platform. In Q4, Cadence released version 12.2 of Incisive. This release provides a 2x improvement in performance, significantly enhanced the buffer capabilities, improved low-power modeling support and new methodologies for mixed-signal verification. Overall, Incisive 12.2 doubles productivity of SoC verification over the previous release.
2012 was also a strong year for our SoC Realization solutions, with revenue growth exceeding 30% for design and verification IP. We continue to gain momentum in design IP. In Q4, we completed an IP contract with Tilera, a fabless semiconductor company that develops the TILE-Gx multi-core processor for networking, video and cloud applications. This included DDR controllers, DDR 5, 10-gig and 40-gig Ethernet and other high-speed interface IPs. Verification IP had another strong quarter to complete a stellar year, which we closed multimillion contracts with semiconductor and system companies.
We are continuing to aggressively expand our design IP and VIP catalogs for the most advanced applications and protocols. In Q4, we introduced the industry-first design and verification solution for the latest automotive Ethernet controller standard. Cadence received a Customer Choice Award from TSMC recent Open Innovation Platform Ecosystem Forum for our work supporting DRAM development, including design IP and verification IP.
Let us talk about System Realization. Our hardware business, led by Palladium XP, achieved record sales in 2012. Primarily due to current economic uncertainty, we expect Palladium sales to remain strong in 2013 but below the 2012 level. As an indicator for the secular increase in the size of our emulation business, total expected hardware sales for the 2011 to 2013 period are 90% higher than the 2008 to 2010 period.
Our PCB and IC packaging product lines continue to see good growth, with revenue up 11% for 2012. We upgraded our product with the release of new versions of Allegro package designer and our system-in-package layout solution that support design of low-profile IC packages for smartphones, tablets and ultrathin notebooks. Integration of Sigrity is on track, with strong demand for its products, driven by increased need for accurate analysis for advanced consumer and data center products.
In summary, Cadence continues to gain momentum in 2012. Before Geoff goes through the numbers, let me leave with you what to look for from us in 2013: continued progress in design solution for advanced process nodes and featuring multi-core embedded processors; growth in mixed-signal and low-power design, driven by mobility, automotive, industrial and emerging [indiscernible] trends; and continued strong demand for verification and hardware solutions, driven by growing design complexity.
With that, I will now turn it over to Geoff who will review the financial results and provide our outlook.