Lip-Bu Tan
Analyst · Benchmark
Good afternoon, everyone, and thank you for joining us today. Cadence delivered strong operating results for Q3. Revenue was $434 million, up 8% year-over-year. Non-GAAP operating margin was 27%, above the high end of our guidance range. Non-GAAP EPS was $0.28 also above the high end of our guidance range. And operating cash flow was $87 million, which keep us on track for our guidance of $360 million for the year. Let us first address the environment. Semiconductor business conditions remain challenging and slower semiconductor growth for the year now appears likely. As we reported last quarter, we remain mindful of the ongoing consolidation in our semiconductor customer base. While we do not expect the material impact on our business near term, consolidation could pose a challenge to industry growth over the next few years. Now let us turn to the Q3 highlights. Our System Design Enablement strategy continues to create new vertical opportunity. In Q3, we signed a significant contract with GE Aviation for IP, hardware and system level design services. A biomedical technology company adopted our low power mixed-signal design flow. We became the provider for the functional verification environment of a leading automotive chip supplier, and a global automotive supplier significantly expanded its contract for functional safety verification to reduce their effort for ISO 26262 compliance. In the digital and signoff space, the theme for the quarter was continued innovation, adoption and proliferation of our new products. We expanded our digital footprint across multiple growing industries and across multiple process nodes. We now have over 30 such customers using the Innovus Implementation System for the advanced-node production designs. This includes seven of the industry’s top 10 semiconductor customers, companies where our digital implementation position has increased significantly. In just three months, since its launch the Genus Synthesis Solution has already been purchased by multiple companies with many more in evaluation. Cypress Semiconductor is standardizing on the Cadence full digital flow and Spectre XPS for full customer verification for their next generation 40 nanometer mainstream products. Innovation continues with the introduction of another digital product, the Joules RTL Power Solution. Joules deliver time based, RTL Power analysis 20 times faster than previous solutions. One of our most exciting announcements of the quarter was that the nano-electronics research institute imec and Cadence completed a takeoff of the world’s first five nano-meter test chip using EUV combined with 193 immersion, lithography and quadruple patterning. In Signoff, our Tempus Timing Solution surpassed 200 tape-outs, while the Voltus Power Solution and Quantus Extraction Solution continue to add new customers. Cadence earned a Partner of the year award from CSMC for joint development of the 10 nano-meter design input infrastructure. IP is the fast growing part of our business. It is one of the key [tenants] [ph] of our System Design Enablement strategy. The new Tensilica vision 5 Fourth Generation imaging DSP was introduced in Q3, which significantly improved capabilities and performance. The Vision P5 already have a major design win, and we believe the vision market present a huge opportunity especially in mobile, data and IoT applications. Design IP had the best quarter ever. Two major customers, a system company and a semiconductor company have adopted our 14/16 nanometer multi-protocol SERDES PHY for production design. Ours is the first multi protocol SERDES PHY at this node. We also released a broad portfolio of design IP for CSMC 10-nanometer FinFET process, for which we already have secure multiple design wins. We received the CSMC panel of the year award for analog/mixed-signal IP. Now, let us turn towards System Design and Verification. Verification remains the fastest growing challenge for our customers, who must deliver functionally correct products within ever tighter market windows. Addressing the Verification problem requires a holistic approach with the integration of multiple, complimentary products which we provide with our system development suite. The suite had a all-time record quarter in Q3, driven by the growth in North America and China. The exciting news for the hardware is that we have begun shipping our next generation emulation platform. Purchases of Palladium XP II, the existing platform continues at a good pace in Q3 with strong sales to system companies. Sales of Protium, our FPGA prototyping platform, ramped significantly in Q3. Formal Verification had a very strong quarter. A large system company renewed and increased adjustment goal capacity by 60%. This was our largest order ever for formal verification. As companies in China move towards the leading edge, they are adopting formal technologies. And in Q3, we have our largest formal verification order so far in China. Our system interconnect business which includes PCB, Security System Analysis and IC Packaging Tools again delivered strong growth with revenue up 9% year-over-year. Our Allegro system in Package Technology now supports TSMC's Integrated Fan-Out packaging technology, also known as InFO. InFO advanced wafer level packaging technology provides cost effective system scaling to increase bandwidth and will be our ideal solutions for mobile and IoT applications. In summary, Cadence continued to deliver strong operating results in the environment that remains challenging. The System Design Enablement strategy is bringing more innovation and an increased vertical focus to our business and solutions. In digital and signoff, we saw continuous innovation, adoptions and proliferation of our new products. We are steadily introducing new products and gaining customers in IP. We have started shifting our next generation emulation platform. And our PCB system analysis and packaging solutions post another strong quarter of growth. Now I will turn the call over to Geoff to review financial results and provide our outlook