Lip-Bu Tan
Analyst · Bank of America
Good afternoon, everyone, and thank you for joining us today. Cadence achieved excellent operating results for the third quarter through consistent execution and broad-based proliferation and adoption of digital and signoff, custom-analog and IP solutions. John will provide more details on this in a few minutes. There is a favorable dynamic that is benefiting the semiconductor industry, EDA and Cadence, driven by growth in emerging technologies trends such as machine learning, IoT, edge computing and autonomous driving. Now let us take a closer look at our highlights from Q3, starting at the customer and ecosystem level. Cadence is collaborating with Xilinx, ARM and TSMC to build the first test chip for Cache Coherent Interconnect for Accelerators, or CCIX, using the TSMC 7-nanometer FinFET process. This chip contains Cadence IP and is designed using a full Cadence design flow. Applications such as big data analytics, search, machine learning and 5G wireless will benefit from CCIX. We signed an agreement with long-time customer, Dialog Semiconductor, where we have grown to become their prime EDA partner based on the strength of our mixed-signal solution, and they are now using our latest products in simulation and digital implementation. In Q3, we extended our collaboration with Hitachi for system design enablement, spanning chip-level to PCB-level mixed-signal designs with thermal analysis, hardware/software codesign, co-verification to address functional safety requirements. InvenSense business unit of TDK that develops sensor SOCs expanded their use of our mixed-signal design solution. TSMC recognized Cadence with 3 Partner of the Year awards for the joint development of both 7-nanometer FinFET Plus and 12-nanometer FinFET Compact design infrastructure as well as for joint delivery of automotive design enablement platform. Now I will move on to products highlights. Digital and signoff revenue grew 15% year-over-year in Q3, driven by increasing proliferation with market-shaping customers and broadening adoption by other customers. In terms of specific highlights. A global marquee company and a key IP partner expanded and deepened their investment in Cadence technology, including our digital solutions. Quantenna Communications, a leader in carrier-class WiFi chips, adopted our full digital flow, including Genus Synthesis, Innovus Implementation and Tempus for timing signoff. More than 80 customers have now deployed our digital and signoff products for advanced node designs, with more than 35 of those for 7-nanometer designs. IP revenue grew 14% year-over-year in Q3 as our refined synergy continues to achieve strong results under the leadership of Babu Mandava. In Q3, we expanded our relationship with a large Asian memory chip maker for LPDDR4, PCI Express Gen4, NAND flash PHYs and Tensilica DSPs, which is the foundation for their next generation platform. We delivered a comprehensive automotive IP portfolio for TSMC's 16-nanometer FinFET automotive process technology that includes our flagship DDR and PCI Express PHYs price and controllers. Tensilica continues to be the market leader for audio signal processing, and adoption is growing for our DSPs that are tuned for vision and neural networks. In Q3, 10 customers licensed Tensilica IP, including 5 in China. Four of the 5 China customers were new. For system design and verification, momentum continue for Xcelium, our parallel logic simulator, which added more than 15 new customers in segments, including mobile, communication, storage and memory. More than 50 customers have now adopted Xcelium. Palladium Z1 is the most advanced emulator in the market. In Q3, building on the comprehensive software relationship, Marvell expanded its investment in Palladium Z1 to extend emulation use to all its engineering projects. The new Protium S1 FPGA-based prototyping system continues to gain traction in Q3 with 17 purchases, 9 of which were repeat orders. Revenue growth has been strong this year for our custom and analog design solutions, up 12% year-over-year for Q3, as increasing complexity is driving increased need of advanced node custom design and simulation solution. Our system interconnect and analysis solutions grew 7% year-over-year for Q3, with growth in PCB implementation, IC packaging and Sigrity power integrity analysis. Before turning to it to John, let me quickly summarize my comments. Consistent execution and broad-based proliferation and adoption of our solution drove excellent financial results. Semiconductors, EDA and Cadence are benefiting from a number of emerging technology trends. Proliferation of our digital and signoff solutions continues to grow with market-shaping customers, and adoption is broadening to other customers. IP growth has rebounded this year to over 10% with our refined strategy. Custom and analog growth is strong as both large and small customers have been adding capacity. John will now review the financial results and provide our outlook.