Brian Faith - President & CEO: Elias Nader - SVP & CFO:

Ladies and gentlemen, good afternoon. At this time, I'd like to welcome everyone to QuickLogic Corporation's Fiscal First Quarter 2025 Earnings Conference Call. As a reminder, today's call is being recorded for replay purposes through May 20th, 2025. I'd like to turn the conference over to Ms. Alison Ziegler of Darrow Associates. Thank you. You may begin.

Thank you, operator, and thanks to all of you for joining us. Our speakers today are Brian Faith, President and Chief Executive Officer; and Elias Nader, Senior Vice President and Chief Financial Officer. As a reminder, some of the comments QuickLogic makes today are forward-looking statements that involve risks and uncertainties, including but not limited to statements regarding our future profitability and cash flows, expectations regarding our future business, and statements regarding the timing, milestones, and payments related to our government contracts, and statements regarding our ability to successfully exit SensiML. And actual results may differ due to a variety of factors, including delays in the market acceptance of the company's new products, the ability to convert design opportunities into customer revenue, our ability to replace revenue from end-of-life products, the level and timing of customer design activity, the market acceptance of our customers' products, the risk that new orders may not result in future revenue, our ability to introduce and produce new products based on advanced wafer technology on a timely basis, our ability to adequately market the low-power competitive pricing and short time-to-market of our new products, intense competition by competitors, our ability to hire and retain qualified personnel, changes in product demand or supply, general economic conditions, political events, international trade disputes, natural disasters, and other business interruptions that could disrupt supply or delivery of or demand for the company's products, and changes in tax rates and exposure to additional tax liabilities. Actual results or trends may differ materially from those discussed today. For more detailed discussions of the risks, uncertainties, and assumptions that could result in those differences, please refer to the risk factors discussed in QuickLogic's most recent filed periodic reports with the SEC. QuickLogic assumes no obligation to update any forward-looking statements or information which speaks as of the respective dates of any new information or future events. In today's call, we will be reporting non-GAAP financial measures. You may refer to the earnings release we issued today for a detailed reconciliation of our GAAP to non-GAAP results and other financial statements. We have also posted an updated financial table on our IR web page that provides current and historical non-GAAP data. Please note, QuickLogic uses its website, the company blog, corporate Twitter account, Facebook page, and LinkedIn page as channels of distribution of information about its business. Such information may be deemed material information, and QuickLogic may use these channels to comply with its disclosure obligations under regulation update. A copy of the prepared marks made on today's call will be posted on QuickLogic's IR web page shortly after the conclusion of today's earnings call. I would now like to turn the call over to Brian. Go ahead, Brian.

Thank you, Alison. Good afternoon, everyone, and thank you all for joining our first quarter 2025 conference call. Last quarter, I said that we expected to be awarded the first of two eFPGA Hard IP contracts for Intel 18A designs within weeks, and the second one very shortly after that. I forecasted the combined value would be mid-seven figures, and if awarded in the expected timeframe, that the revenue would be recognized in Q2. The first of these contracts was awarded a few weeks ago after our last conference call, and on April 28th, we announced that we delivered design-specific eFPGA Hard IP for the customer's Intel 18A test chip. The second contract is with the same customer, but for a different program. The customer has advised us that it has been awarded funding for the program, but funding for the production ASIC, which is a subcomponent of the program, will not be awarded until Q4. Due to this delay, our revenue guidance for Q2 is $4 million. While disappointing, it does not change our full-year outlook for solid revenue growth, non-GAAP profitability, and positive cash flow. Let's take a moment to discuss the test chip program. Given the fact Intel 18A is a new process and incorporates some state-of-the-art features, such as power via back-site power delivery network that we are using in our eFPGA Hard IP we determined having a test chip would be a good investment. To do a test chip on our own would have cost millions of dollars, so we contributed our eFPGA Hard IP license in kind for access to the customer's test chips. These test chips will enable us to fully characterize the power consumption and performance, which enables lead prospective customers to lower their risk assessment of our eFPGA Hard IP on…

Thank you, Brian, and good afternoon, everyone. Total first quarter revenue was $4.3 million, and approximately $300,000 above the midpoint of our guidance range. This upside was driven by a customer that pulled in new product shipments to Q1 that were previously scheduled for Q2. Total revenue was down 28% from Q1 2024, and down 24% compared to Q4 2024. New product revenue in Q1 was $3.8 million, down 23% from Q1 2024, and down 19% compared to Q4 2024. Mature product revenue was $0.6 million, down from $1.1 million in the first quarter of 2024, and $1 million in the fourth quarter of 2024. The decreases in total revenue and new product revenue from prior periods were mostly due to the timing of certain large eFPGA IP contracts. Non-GAAP gross margin in Q1 was 45.7%. This was below the midpoint of our outlook due to the fact approximately $300,000 of R&D costs that we projected would be allocated to OpEx were allocated to COGS. This compared with non-GAAP gross margin of 71.3% in Q1 2024, and 62.9% in Q4. Non-GAAP operating expenses in Q1 were approximately $3 million. This was approximately $200,000 below the midpoint of our outlook, and due to the COGS allocation I just mentioned above. This compares with non-GAAP operating expenses of $2.5 million in the first quarter of 2024, and $2.9 million in the fourth quarter of 2024. Non-GAAP net loss was $1.1 million, or $0.07 per diluted share. This compares to non-GAAP net income of $1.7 million, or $0.12 per diluted share, in Q1 2024, and a non-GAAP net income of $0.6 million, or $0.04 per share, in the fourth quarter of fiscal 2024. The difference between our GAAP and non-GAAP results is related to non-cash, stock-based compensation expenses, and restructuring costs. Stock-based compensation…

Thank you, Elias. As I mentioned earlier, I was selected by Intel to present the QuickLogic story from the main stage at Direct Connect 2025. My presentation was very well received, and based on the feedback we were given, gave our core value proposition a huge shot of credibility. If you boil down our value proposition to just one thing, that thing would be enabling integration, and that is what has driven the semiconductor industry since the IC was invented 65 years ago. Our primary target markets are designs that would typically have a discrete FPGA sitting next to an ASIC or SoC. That is a very common practice in USMAG designs, where discrete FPGA revenue was approximately $1.5 billion in 2024. This market opportunity, the very high qualification cost DIBs have for every discrete device, and their intense focus on SWAP-C, size, weight, area, power, and cost, are the reasons we prioritized USMAG as we built our foundation for eFPGA Hard IP If you review the Faraday website, you'll see this pairing of a discrete FPGA with an ASIC or SoC is also more common than you might think in commercial designs. We believe the Faraday FlashKit development platform that integrates our eFPGA Hard IP in its SoC will lead to a number of contracts in commercial markets. Also intriguing to note about Faraday's success is its very tight focus on storefront. Faraday manages storefront services for the vast majority of its contracts, and with that, reported nearly $0.5 billion in revenue over the trailing 12 months. To be clear, our sales through Faraday to its customers will be eFPGA Hard IP contracts. However, we believe a growing number of our direct IP customers will have interest in QuickLogic handling storefront services. As a matter of fact, we booked our first direct-to-storefront contract earlier this year, and we have several contracts we believe will end up being storefront. We see this as a trend for QuickLogic. As we have tried to outline for you in this call, 2025 has started out more slowly than we anticipated. However, beneath the numbers, momentum is building rapidly, and we are confident that we will post solid revenue growth, non-GAAP profitability, and positive cash flow for a full year 2025. Not only that, we also believe we will build momentum throughout the year to set us up for solid growth for years to come. Thank you. I'd now like to open the call for questions.

Thank you. We will now be conducting a question-and-answer session. [Operator Instructions] The first questioner is from Quinn Bolton from Needham & Company. Please go ahead.

Thanks for taking my question. Brian, maybe just talk us through the ramp of Intel 18A. You guys have done a couple of test chips. Now as that starts to move to production, is your revenue stream mostly just royalties on the customer solution and being also just aggressive? Is this customer starting in commercial markets? Or is it more of a defense or risk-based application? And then I've got a follow-up. Thanks.

Hey, Quinn, the audio is a little garbled, but I think if I repeat the question, you're asking about sort of the progress of Intel 18A in general and our timing of different IP that we've done for that leading up into revenue and royalties in the future. Is that right?

Yeah, that's right. Sorry for the background noise.

Okay. Yeah, so I guess if we rewind a year when we first got access to the PDK Version 1.0, this was definitely the first time that we designed something on this modern of a process technology, this sort of state-of-the-art. Definitely took a lot from our team to get that going, a lot of EDA tools, a lot of focus on that. But once we had it ported to that technology we started to appreciate some of the capabilities of it, like the power via backside power that I mentioned earlier. That was one of the basis of our presentation at the Intel Direct Connect last week or two weeks ago. And we realized that you could actually we got a really good IP core out of this in terms of power and die size because of those capabilities that we took advantage of. And I think that as we started engaging more primarily with the defense industrial base, they're looking for things that are, I would say, further down the TRL curve than just paper tigers or PowerPoint. And when I say TRL curve, I'm talking about technology readiness level. It's from one to nine. One is through your paper simulations and nine is your in-flight on things. So by us participating in this test chip that we've talked about, this actually helps accelerate further down the TRL curve in the eyes of prospective customers, especially defense industrial base ones. And I think that that was sort of the tipping point where we're able to carry these additional customer conversations forward into more timing-related discussions, commercial-related discussions, and understanding when they're planning to tape out their own test chips. So I think that's all to say that we do have 18A license revenue forecasted this fiscal year, not…

The value of the test chip, my guess is it's a certain size fabric that you're testing out on the test chip. The fact that you're just testing out a sort of given size fabric is enough to convince other customers that says, hey, this is real, it's working. And if we change the size or the configuration, it's still enough in terms of their eyes to sort of give them a confidence to move forward on new designs.

It absolutely is because once you prove out a common denominator for the logic and the routing and the memory and the DSP blocks, most customers believe that if you can do that for that size, that if you need to stamp and repeat a bigger array size for them, that we can do that. And they know that that's sort of our model with Astralis. We're sort of making almost like a memory compiler out of it for FPGA technology. So once we prove out the first one for power and timing, that's all stamp and repeat for bigger array sizes. And the beauty of our models, we can do that in a matter of weeks, which is well within the cycle of what they need to do for an 18A type ASIC.

Got it. And then the second question I had, just so you guys are looking for profitability for the full year, obviously a strong revenue ramp. Just wondering if you could kind of, what are the two or three maybe biggest drivers of that revenue ramp through the year. Obviously you've talked about Intel 18A revenue. You've talked about the Rad-Hard contract. What are the key programs that drive that nice revenue growth into the second half? Thank you.

Yeah, I can take that. So our base business that's here every quarter is our ongoing Antifreeze FPGA business, what we call mature products, and then the strategic Rad-Hard contract. And with that contract that we signed for the Rad-Hard contract last December, and then the incremental funding modification that was added on top of that in the last few months, we have good visibility of that program for the rest of this year. So the new revenue, the new winds driving the strong second half growth, we are forecasting income from these IP contracts, some of which are just IP and some of which are storefront. And I think this, again, if you look back in history, last five years ago, that's going to be a lot of designs you need to close to get to that number. But then if you drill into, okay, in the last year, you've come out with two 12 nanometer process ports, and now you've got this one for Intel 18A. All of those have substantially higher average selling prices than the stuff that we were doing years ago on 22 and more mature nodes. And so you don't have to close a lot of designs to get strong revenue growth. And like I was just answering on your first question, we are seeing a lot of strong interest on Intel 18A now. Now that people realize that we're done with the first port, and those have substantial price increases or the value of those is much higher. And so we're seeing a handful of designs, again, both on 12 nanometer and 18A driving that second half revenue growth. And very well manageable within the team size that we have, again, because we have this whole notion of Australis being a very automated way of taking the port that we've done and then adapting it for customer and design-specific IPs that we need to come out with.

Thank you, Brian. Thank you, Elias.

Next question is from Rick Neaton from Rivershore Investment Research. Please go ahead.

Hi, Brian. Hi, Elias. Thanks for taking my questions tonight. My first question is you mentioned in your closing remarks, Brian, about several storefront opportunities. We know about one, which is the direct-to-storefront you announced, and you've also mentioned that the Strategic Rad-Hard contract could lead to storefront. Can you provide any color on what other opportunities you have for storefronts percolating in your funnel or in the itemized list of projects you've already provided?

Sure. Just to add one more to that list that you gave there, Rick, we have the November 2022 tape-out customer. Between that and this more recent one that we just announced on the last call, the direct-to-storefront, and, of course, the biggest of which is the Strategic Rad-Hard opportunity, those are contracted ones. If we move to things in the funnel, we have a handful of ones that we've either proposed through the government RFP process, where people are looking at seeding different technologies to help build a chiplet ecosystem. We have that. There's ones that have come about now since, at the Intel Conference, they launched their own chiplet alliance or ecosystem, and we're one of the founding members of that. And there's been a lot of interest coming out of that for chiplets that are now part of our funnel. But I think because, again, we have IP ready now on 12 and 22 and now 18A, we can actually help people with their chiplet designs without having to do a port first. And if you think about the economics here, the more advance you get in the process technology, substantially higher investment is required to do these designs and tape-outs between IP and EDA tools and mass costs. And so there's a much higher bar now to do a chiplet or do a chip, and so if there's reuse that you can design into it, it's really perking people's ears up on how to do that, and that's where I think the eFPGA has a lot of value. And so, yeah, like I said, there's several opportunities that we're tracking now, some of which are new, coming out of the Intel Direct Connect conference around that, that we can be good participants in, either as IP or doing the full design ourselves.

Okay, thanks for that explanation. That's helpful. You talked about the $1.5 billion FPGA market in USMAG, and your unique value proposition is enabling integration. Is the catalyst that you think you will be, that will enable you to make a dent into that addressable market, the ability to lower the cost of verification of a product? I think you mentioned that each military use case has to be verified, and yet it sounds like you can reduce the cost of verification to a per-chip verification. Is that where you're going with that?

Yes. So if we step back for a moment, that $1.5 billion obviously is a big number, and I'll give some foreshadowing if you want to go watch the video that we post later, but I give some more statistics in that presentation. But almost 75% of DoD systems use FPGAs today, so it's not a lot of money in a few systems. It's a lot of money in a lot of systems. And almost all of these systems are also doing ASICs, custom ASICs or SoCs by the Defense Industrial Base. Then why are they doing ASICs? A lot of times they're doing ASICs because they can't quite get functionality out of standard products that they need for the mission. It could be that they need to have something that's of the critical nature that's designed and manufactured onshore, whereas I think almost all, if not all, FPGAs today are manufactured overseas, so there's a national security aspect to this. It could just be that they need to obfuscate their IP, and they can't do that in standard products that have well-documented backdoors into the bitstream. It could also be that they're looking to lower SWAP. I mentioned that here today. I also talked about it in the presentation. SWAP is an abbreviation for size, weight, and power, and sometimes people add cost to that to make it SWAP-C. So those are all legitimate reasons why the Defense Industrial Base is looking at doing ASICs, and again, why would you do $150 million ASIC and then go buy a lot of FPGAs and stick it right next to that same ASIC. If you have the opportunity to integrate that into that same chip, not only are you going to get lower SWAP-C by having it all integrated together, yes,…

Okay. One final question. Faraday was originally part of UMC, or came from UMC?

It was a spin-off, yes.

Are your opportunities with Faraday limited to the node that the part that was announced works on, or are you looking at maybe going smaller, like at the 12-nanometer node that UMC is working with Intel on?

I would love to go smaller. Obviously, we have a big focus on selling what's available today, and so there's a big focus on doing what we can do and helping them with the 22 nanometer. It's probably like they're doing something on 12 with UMC, and I think that the more comfortable that they get, they being Faraday, with this notion of embedded FPGA in a SoC, the more amenable it is to jump to that next node. And the next node is probably not just for cost reasons. It's going to be for use case and applications and end markets. So whereas 22 nanometer is great for low-power edge computing, 12 nanometer is probably going to be a little bit better at some other applications, more compute-intensive. And so we do every engagement, every partnership we enter into, we think about, yeah, there's this first step, like in the case of this 22 nanometer one. But what could it lead to? There's a huge investment by both companies to get this thing working. And so we want to see that it's portable to the next thing, and 12 is clearly one of those. And then I was pleasantly surprised to see them at the Intel Direct Connect as one of the folks doing 18A stuff. So everything that we're doing now with 22, architecturally, software-wise, business model-wise, that all leads to what we could possibly do on the Intel 18A node, which I think is a very pleasant surprise.

Thanks, Brian. Thanks, Elias.

Thanks, Rick.

Next question is from Richard Shannon from Craig Hallam. Please go ahead.

Thanks, Brian and Elias, for taking my questions. Brian, I guess the first question is, this $1.5 billion of FPGA revenues for USMAG, I think the way that you referred to it made it sound like it was just for Intel 18A-related stuff here, but it seems like the Strategic Rad-Hard would also kind of cover the same thing. So I just want to clarify, what is that exactly covering?

So that's an estimate of total FPGA usage by the USMAG on an annual basis, not specific to 18A. So my apologies if I gave that impression. That's the annual programmable logic market today in revenue. Now, the Strategic Rad-Hard one would obviously fall under discrete FPGA, but the market that that is also trying to go into is not just limited to the FPGA market today, because that part is actually doing something that's not available today from FPGAs. To get to some of the capability that we're designing into that, you would actually have to go to your own ASIC. So from a total market perspective, it would actually be the FPGA plus the ASIC market or some percentage thereof that would be the served available market for that specific device.

Okay. That makes sense. That's helpful. Okay. Now I understand that a little better. Thanks for clarifying that one. Let's step over to the Rad-Hard program here. And I was typing so fast here, I may have mistyped or something here, but I guess my core question here is trying to get a sense of when you think we're going to start to see storefront revenues pop up here. I get the sense that it could have been maybe talking one or two years ago, it could have been like counter ‘26 or ‘27. Is that still fit your general timeframe or how do we think about this?

So we're waiting into areas that I have asked for permission to share, and I've been denied that request. So I can't give hard years as dates as much as I would like to, but let me try to give some contextual information and you can draw your own conclusions. So I think that we've been doing this development since August of 2022. And when we signed that first contract, it was outlined as a four-year development. And at the time I was also allowed to say that there's two chips contemplated in this contract, a test chip and a final chip, much like you would normally do in any development. And in more recent calls, I have talked about, I think a lot more engagement with the defense industrial base, which means the end customers and getting closer and closer in milestones to being able to get them something that they can actually start evaluating with their own designs. So I'll just reiterate that like I just did from a programmatic perspective and you can draw some conclusions from that. But I'm definitely spending more time now than I was a year ago directly with defense industrial base folks around this program and doing that in a way that we can make sure that we have folks lined up for when devices are available, test chips are available for them to start exercising with their own designs, which would include devices and our user tools.

Okay. I'll look forward to the time when you actually get permission to talk about that. That'll be a very interesting conversation. Maybe touching quickly on Faraday, probably more of a clarification. I was just rereading your four takeaways from this and I just guess I guess I just want to make sure the revenues you're not expecting any storefront revenues from Faraday directly, but you're using it to underscore the storefront business model. Is that okay?

That's what I thought, but I just to Faraday it will be licensed and royalty because they're the ones ultimately selling a storefront device to customers. Our point in bringing them up is I think it's a very good exemplar for the storefront model where you start as services and IP, but ultimately are providing the supply chain services to the customer so that what you sell them or ship them as a finished good and they don't have to invest in the supply chain resources and foundry and packaging relationships to get that done.

All right. Maybe my last question here, and I made this from either of you. I think you've talked about from a yearly perspective here, getting to profits and gross margins. I think it's 60% or something like that, but you talked about solid revenue growth I think was a term at least you used last quarter. Anyway, you'd want to give us a sense of what that means quantifying. I mean, is it something similar to what you were hoping for last year, which I think was 30% just to any way you want to help us level set a little bit.

Well, it's not 30%. It's Elias, by the way, Richard. It's not 30% for sure, but since we don't give a yearly outlook, I'll tell you, we're expecting a decent rebound in a second half. Let's put it this way. That gives us that, that confidence to be profitable and to end the year with a cashflow positive.

I think that is going to be all for you guys. Thanks for taking my questions.

Thanks, Richard. Our next question is from Martin Yang from Oppenheimer. Please go ahead.

Hi, thank you for taking the question. My first question is a follow up on Faraday. So in this partnership, do you expect Faraday to take on the majority of the go-to market to sell the chip? Are you taking on any sales responsibilities?

They will be the primary interface to their customer. As they're talking to system companies that are wanting to do ASIC design, because embedded FPGA is not just a USB core, as an example, and there are software tools involved in a customer using the embedded FPGA. We are definitely right behind Faraday, enabling their sales force with different use cases and documentation and training. So that is a cohesive sell to the end customer. So Faraday will be the point person, if you will, for those customer engagements directly.

Got it. And can you give us a sense of the most applicable end markets or devices that those chips will go into?

Yeah, their focus is around low power, industrial and IoT applications. If you look at what they've said publicly about this development kit, and we actually had this at our booth at the Intel conference last week, it runs an operating system, it's got a display and it has memory on the board. And the level of processing is definitely more than just the basic micro controller. So you could run some pretty good applications, including running a full operating system with a user interface and GUI. So I think it would be applicable for low power edge applications. And just for further clarification, one of the use cases that we actually had discussed prior with them was what we had talked about previously when we did our Arnold chip on 22 FDX, where we were able to reduce the energy consumption of Edge AI applications like human presence detection. And that I think will be one of the demos that's actually provided to customers as a use case using that platform. It was actually architected to do things like that very well.

Thanks, Brian. That's it for me.

Okay. Thanks Martin.

This concludes the question-and-answer session. I'd like to turn it back to Brian Faith for any closing comments.

Yeah. Thank you for joining today's call. Before we conclude, I'd like to highlight a few upcoming events where QuickLogic will be participating. May 21st, the Ladenburg Technology Innovation Expo in New York. If you are interested in meeting with us there, please contact Alison for details on how to register. June 23rd, we'll be at the Chips and Systems Conference, formerly known as DAC, in San Francisco. And on July 14th, we will be in Tennessee at NESREC, N-S-R-E-C. That's the Government Radiation Effects Focus Show. We hope to see you at these events. As always, we appreciate your time, interest, and continued support. And we look forward to sharing our continued progress with you in August. Thank you and goodbye.

This concludes today's teleconference. You may disconnect your lines at this time. Thank you again for your participation.