Aart J. de Geus
Analyst · Needham & Company
Good afternoon, and thank you for joining us. I am happy to report that in Q1, our business, technology progress and customer engagements were strong across the board. We met or beat every target we communicated last quarter, achieving revenue of $475 million and non-GAAP earnings per share of $0.67. As a result of this excellent start to the year, as well as reinstatements of the federal R&D tax credit, we're raising our non-GAAP earnings per share outlook for fiscal 2013 to a range of $2.35 to $2.40, up solidly from our high single-digit guidance into double-digit growth. Brian will provide more financial detail in just a minute. Before discussing some highlights, let me briefly comment on the customer landscape, which fundamentally has not changed much from last quarter but benefits from a slightly more stable macroeconomic outlook. Against this backdrop, we see the semiconductor industry continuing a very aggressive push, both in terms of technology and efficiency. The technology drive is motivated by companies seeking to differentiate themselves by adopting a wave of emerging new semiconductor capabilities. The efficiency push addresses the challenge of delivering these new technologies under aggressive product cycle and cost requirements. The EDA industry, and Synopsys in particular, is a key partner in these quests. Increasingly, customers see their EDA relationship as an essential differentiator in their market battles. Although difficult to generalize in our very competitive landscape, we do sense a bit of improvement in the pricing environment and business terms. The corollary to my comment on differentiation is this. Customers and suppliers increasingly realize that to navigate the intersection of advanced technology, unforgiving time to market and intense competition, close collaboration is essential. Synopsys' focus on both points tool [ph] leadership and integrated solutions makes us a desirable supplier, and our collaboration with advanced customers and key partners continues to yield great results. Just last week, for example, we further expanded our broad collaboration agreement with ARM to include the latest ARMv8 processor models. Working with mutual customers, Synopsys and ARM jointly accelerate product development cycles around ARM's latest processors. State-of-the-art collaboration relies on the constant delivery of new capabilities, so let me provide some recent product highlights. On the implementation side, Synopsys supports a continued aggressive adoption of more complex design nodes. Simultaneously, we see a fundamental discontinuity in the structure of the transistor. We're closely working with silicon providers to roll out evolving technology to address these challenges. With the structure of the transistor itself migrating from horizontal to new vertical FinFETs, better power and performance open the door to great new applications. It also brings about a slew of technical challenges in EDA and IP, challenges for which Synopsys is particularly well equipped, again making us a key partner in our customers' future differentiation. As an example of how customers rely on us, 90% of 20-nanometer and below tape-outs today have used Synopsys implementation, while we're already working with some all the way back down to 10 nanometers. Synopsys is the only EDA company that has been investing for many years in FinFET enablement throughout our portfolio, from 3-dimensional TCAD simulation to photolithography to manufacturing tools, to physical placement, routing, extraction and verification, to circuit simulation and custom design, all the way to sophisticated IP libraries, memories and building blocks. A good example of multiyear collaboration in this area is with Samsung, where we successfully taped out the first test chip on their 14-nanometer low-power process. Samsung chose Synopsys as its FinFET partner because of our successful 20-nanometer collaboration history and our comprehensive FinFET focus throughout our portfolio. As advanced transistor research accelerates, demand for our 3D TCAD products continues to grow. For example, during the quarter, we expanded our collaboration with Imec, a world-leading research center, to jointly optimize FinFET technology for 10-nanometer and below design. Multiyear collaborations have not only yielded a number of advanced tape-outs, but today, we are also selling our own FinFET-based embedded memory libraries and logic IP. Finally, through the acquisition of SpringSoft, we also have a FinFET-ready custom implementation solution. Notwithstanding the emphasis on advanced technology, our business with customers who are focused on more established nodes is also strong. These customers invariably squeeze performance, power and area out of their chips to be competitive. We recently demonstrated that advances made in our leading-edge tools have great impact on established nodes as well, most notably in run time and capacity, which is a good transition to the topic of verification. The move to smaller transistors also enables the other side of Moore's Law, many more transistors. Indeed, the overall complexity of not only chips but systems of chips is precisely what makes continued end product innovation possible. Verifying these products is the largest bottleneck in electronics. Just looking at the latest smartphones, one finds multiple multicore processors with hundreds of millions of transistors coupled with complex operating systems, applications, networking and wireless protocols. Not only is the hardware complex, but so is the interaction of the hardware and the software. Solving these verification challenges has been a major focus for Synopsys for many years. Today, we are the market leader in both leading-edge digital verification with about 70% of advanced designs using -- utilizing Synopsys and analog simulation, where 80% of the designs rely on our tools. VCS, which continues to grow well, is the fastest simulator on the market today. With the acquisition of EVE, we also have added the fastest hardware emulator, and combined with our HAPS FPGA boards, we cover the entire hardware validation and hardware software verification space. With the acquisition of SpringSoft, we've added to our portfolio the most compressive open debug system, thus, addressing the entire verification market with outstanding point tools. We have started to combine the best features of these, and we're driving integration of all the elements into a full-line verification solution. Initial customer reaction has been strongly positive, as we have quickly asked for feedback from them. We're now well into the process of developing and communicating combined roadmaps. Both the EVE and SpringSoft integrations are progressing very well. The third area I would like to briefly highlight is IP and Systems, which now represents 1/4 of our revenue. We're the second largest IP vendor with approximately 1,400 IP engineers worldwide designing the most complex IP blocks, importing to all key foundry processes. After 15 years of investment, our DesignWare IP is shipped in more than 1 billion chips per year. Every 2 days, a chip is taped out using our USB. Every week, a chip tapes out with our PCI Express, and customers have already delivered tens of millions of chips containing our 28-nanometer IP. Today, Synopsys is the #1 vendor in interface cores, analog IP and embedded memories. And the market for more IP, including the sub-20-nanometer nodes, continues to expand. We intend to grow our IP business at double-digit rate while gradually increasing its profitability, as we've successfully done in the last 2 years. In systems, we're seeing momentum in both software and hardware-based prototyping. This is promising as we've invested in this area for a number of years, believing that hardware/software verification, as well as the ability to develop software earlier in the process would grow in importance over time. This quarter, 2 large and influential electronic companies increased deployment of virtual prototyping, driving good run rate growth. As the key enabler to early modeling of chips for software development, we expect virtual prototyping to grow gradually and become more mainstream as system complexity emerges as the weak link in time to market. Bridging between systems and verification, our earlier mentioned FPGA-based prototyping systems, HAPS is doing very well also. With a who's who of customers, our newly launched HAPS-70 Series, which uses the most advanced FPGAs on the market, was named Electronics Design's 2012 EDA Product of the Year. In summary, Synopsys is doing very well in all dimensions: technology progress, customer collaboration and financial execution. In Q1, we delivered results that serve as an excellent start to the year. And as a consequence, we're raising EPS guidance to reflect confidence in our outlook. I will now turn the call over to Brian Beattie.