Thank you, Peter. I wanted to focus my last comments on the company trajectory, which both Peter and I supported for all these years and which is based on a very simple strategy executing around a huge R&D investment for technology leadership. This leadership hinges on 4 projects basically at this moment. The first project is a relentless, continuous improvement of our XT and NXT architectures, so basically today, immersion. Now Project 2 is a buildup of an application product suite, enabling and differentiating the NXT products. Project 3 is introduction of the next-generation, game-changer technology, this is the EUV, which will be required by the industry for the next 15 to 20 years. And the Project #4 is the capability to insert costs effectively when the industry requires it, the next wafer size, 450 millimeter, so far planned for production not before 2018. So on Project 1 and 2, as you saw from the press release, we are, again, proving our leadership case with our new NXT:1970, which is to be introduced in H2 of this year. This is a 250-wafer per hour system, with overlay having been achieved down to 1.9 nanometer. And with a suite of applications, product package is valued this year at above EUR 350 million of sales and growing further and fast. With these capabilities, we will be benefiting from current semiconductor process complexities for 20-nanometer logic in DRAM. And these processes are more litho-intensive than ever and from the added complexity of inserting FinFET transistors at the same pitch, which will be called 14-nanometer or 16-nanometer. Even the complexity of vertical NAND which, although on paper, should not require state-of-the-art lithography, in practice, however, requires significant risk-reducing, best overlay and focus capability and requires significant numbers of system as NAND chips volume grows. On Project 3, which is EUV, we made fundamental in the first half of 2013. We have now enough data to confirm the possibility to ramp system in production in 2015 for semiconductor production in 2015 and '16. So I know a question has been asked about the progress of power and et cetera during the quarter, but I want to remind the audience that this quarter was a quarter of transition between the platform 3100, which was limited in power to about 55 watts, to the new architecture, 3300. So this is basically what has happened in the quarter. And within this quarter, we've been able to accumulate certain numbers of data, like that we have now more than 44,000 wafers processed in the field. We have checked further the source potential concept in the lab. We have factory experiments on the new source, a concept called MOPA PrePulse. The new NXE:3300 scanner, which I just talked about, have confirmed 10-nanometer logic and 1x nanometer DRAM overlay and focus capability. More importantly, even the EUV light sources are now running, I would say, routinely at 55 watts, with production-worthy dose control. So this is an equivalent of the machine capable of 40 wafers per hour in the production of NAND. So this performance supports our targeted production throughput for 2014 of 69 wafers per hour, upgradable within 2 years to 125 wafers per hour. This is our commitment to the customers since about a year or 1.5 years. So the current EUV data, the current progress is basically triggering now customer decisions. In logic, 1 or 2 layers of EUV for the so-called 10-nanometer node will deliver already significant die shrinkage compared to any alternative technology inclusive of double patterning or triple patterning. This die shrink will improve the cost of the die, obviously, the power consumption capability and the speed. This justifies -- this value, the shrink factor, justifies EUV as a good technology, even if the throughput of EUV machine is lower even than our 2015 commitment. If, however, the throughput of 69 wafers per hour upgradable to 125, as we committed, does materialize in time as expected, then more EUV layers in logic, up to 7 layers, will deliver process control, yield and cost savings. So first, you have shrink, die shrink, which is 1 or 2 layers. And in addition, you would have your process control, yield and cost saving. And this capability will also enable the technology of EUV to be used on 3 layers in DRAM. So these 2 facets are fundamental to understand, in fact, what will come later. The 3 technology demand drivers that we just mentioned, if we hit the throughput targeted of 125 wafer per hour, we would expect to ship maximum -- our maximum EUV capacity of 25 to 30 tools in 2015. After the current throughput of only 40 wafers per hour, we could still plan to ship 12 to 15 EUV tools, which will be, in fact, used for these 1 or 2 layers of logic, which are compensating emerging tool volume for the layers not handled by EUV. So to finish, I would like to say that it has been my great pleasure to have met many of you over the 9 -- the last 9 years. I would like to thank you for your support of our business model, as measured by your very, very, very detailed interest in lithography. I wish you all the best and I certainly hope that our path will cross again.